Intel Corp. Work Address
Ronler Acres 3
2501 NW 229th Avenue
Hillsboro, OR 97124
USA
Home Address
20539 SW Kirkwood St
Beaverton, OR 97006
Phone: (503) 724-0882
Samuel Palermo
I am currently a Senior Analog Design Engineer in the Advanced Design Group at Intel Corp., Hillsboro, OR. My work focuses on the research and development of high-speed serial I/O architectures, communications techniques, clocking schemes, and circuits for energy efficient parallel optical and electrical chip-to-chip links.
I received my Ph.D. in Electrical Engineering from Stanford University, where I was a member of the VLSI Research Group led by Professor Mark Horowitz. My dissertation work was on the design of high-speed energy-efficient CMOS optical interconnect transceivers.
I am originally from Texas, where I attended Texas A&M University for my B.S. and M.S. EE. At A&M, I worked in the Analog & Mixed Signal Center. Gig em, Aggies!
For more about my academic and industrial experience, please check out my CV.
Research Interests
My primary research interests consist of optimization, design, and implementation of high performance mixed-signal circuit architectures in nanometer CMOS technologies. Specifically, I am interested in- High-speed electrical and optical chip-to-chip communication circuits and design methodologies
- Design and modeling of clock generation and recovery circuits (PLL/DLLs)
- Overcoming increasing variability in analog circuits with digital assistance
Teaching Experience
Teaching Assistant, EE325 - Electronics, Texas A&M University, Spring 1998 & Summer 1999Teaching Assistant, EE214- Electrical Circuit Theory, Texas A&M University, Fall 1997
Publications
High-Speed Optical Links
S. Palermo, A. Emami-Neyestanak, and M. Horowitz, A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects, Accepted in IEEE Journal of Solid-State Circuits.E. Mohammed, J. Liao, A. Kern, D. Lu, H. Braunisch, T. Thomas, S. Hyvonen, S. Palermo, and I. Young, An Optical Hybrid Package with an 8-channel 18GT/s CMOS Transceiver for Chip-to-Chip Optical Interconnect, Accepted in SPIE Photonics West, Jan. 2008.
J. Roth, S. Palermo, N. Helman, D. Bour, D. Miller, and M. Horowitz, An Optical Interconnect Transceiver at 1550nm using Low Voltage Electroabsorption Modulators Directly Integrated to CMOS, IEEE-OSA Journal of Lightwave Technology, Dec. 2007.
S. Palermo, Design of High-Speed Optical Interconnect Transceivers, Ph.D. Thesis, Stanford University, Sep. 2007.
S. Palermo, A. Emami-Neyestanak, and M. Horowitz, A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects, IEEE International Solid-State Circuits Conference, Feb. 2007.
J. Roth, S. Palermo, N. Helman, D. Bour, D. Miller, and M. Horowitz, 1550nm Optical Interconnect Transceiver with Low Voltage Electroabsorption Modulators Flip-Chip Bonded to 90nm CMOS, IEEE-OSA Optical Fiber Communications Conference, Feb. 2007.
S. Palermo and M. Horowitz, High-Speed Transmitters in 90nm CMOS for High-Density Optical Interconnects, IEEE European Solid-State Circuits Conference, Sep. 2006.
A. Emami-Neyestanak, S. Palermo, H. Lee, and M. Horowitz, CMOS Transceiver with Baud Rate Clock Recovery for Optical Interconnects, IEEE Symposium on VLSI Circuits, June 2004.
High-Speed Electrical Links
H. Lee, C. Yue, S. Palermo, K. Mai, and M. Horowitz, Burst Mode Packet Receiver using a Second Order DLL, IEEE Symposium on VLSI Circuits, June 2004.Electrical & Optical Clock Generation
D. Miller, A. Bhatnagar, S. Palermo, A. Emami-Neyestanak, and M. Horowitz, Opportunities for Optics in Integrated Circuits Applications, IEEE International Solid-State Circuits Conference, Feb. 2005.S. Palermo and J. Pineda de Gyvez, A Multi-Band Single-Loop PLL Frequency Synthesizer with Dynamically-Controlled Switched Tuning VCO, IEEE Midwest Symposium on Circuits and Systems, Aug. 2000.
S. Palermo, A Multi-Band Phase-Locked Frequency Synthesizer, M.S. Thesis, Texas A&M University, Aug. 1999.