People

Administrator

Teresa Lynn

Assistant to Prof. Horowitz

Gates 310,
(650) 724-6540

Graduate Students

Name	Research Interests	Office	Email
Valentin Abramzon	Power Supply Noise Measurement, Mixed Signal Circuits	CIS 216
Fernando Amat	Cryo-Electron tomography	Gates 330
Omid Azizi	Energy-Efficient Microprocessor Design / Architecture Optimization	Gates 452
Amin Firoozshahian	Computer Architecture, Smart Memories	Gates 318
Kyle Kelley	Smart Memories, Chip Generator, Circuit/Architecture Optimization	Gates 320
Frances Lau	Biomedical circuits	Alway M001
Farshid Moussavi	Cryo-Electron tomography	Gates 330
Bita Nezamfar	Circuit design, power supply integrity	CIS 216
Dinesh Patil	Digital Circuit Optimization	Gates 448
Ofer Shacham	Computer Architecture, Smart Memories	Gates 320
Xiling Shen	High Speed Link, VLSI	CIS 216
Alex Solomatnikov	Computer Architecture, VLSI design, Smart Memories	Gates 318
Eino-Ville (Eddy) Talvala	Projector and Camera Arrays	Gates 376
Megan Wachs	Computer Architecture, Smart Memories, Chip Generator	Gates 328

The mailing address for Gates is: 353 Serra Mall, Stanford, California 94305
The mailing address for CIS is: 420 Via Palou Mall, Stanford, California 94305

Alumni

Name	Thesis Title	Contact Information
Amir Amirkhany	Multi-Carrier Signaling for High-Speed Electrical Links
Elad Alon	Measurement and Regulation of On-Chip Power Supply Noise
Bharadwaj Amrutur	Design and Analysis of Fast Low Power SRAMs	Greenfield Networks
Jules Bergmann		U.S.A.F.
Tom Chanak	Netlist Processing for Custom VLSI via Pattern Matching
Kun-Yung Chang	Design of a CMOS Asymmetric Serial Link
Mark Dean	STRIP: A Self-Timed RISC Processor
Bill Ellersick	Data Converters for High Speed CMOS Links
Azita Emami-Neyestanak	Design of CMOS Receivers for Parallel Optical Interconnects
Jim Gasbarro	Architecture for High-Performance Single-Chip VLSI Testers	Rambus
Ricardo Gonzalez	Low-Power Processor Design
David Harris	Skew-Tolerant Circuit Design
Richard Ho	Validation Tools for Complex Digital Designs
Ron Ho	On-Chip Wires: Scaling and Efficiency	Sun Labs
Mike Johnson	Super-Scalar Processor Design	AMD
Russell Kao	Piecewise Linear Models for Switch-Level Simulation	Sun Labs
Hema Kapadia	Partitioning-Driven Convergence in the Design of Random-Logic Blocks
Jaeha Kim	Design of CMOS Adaptive-Supply Serial Links
Francois Labonte	A Stream Virtual Machine
Hae-Chang Lee	An estimation approach to clock and data recovery	Rambus
David Lie	Architectural Support for Copy and Tamper-Resistant Software
Dean Liu	A Framework for Designing Reusable Analog Circuits
Ken Mai	Design and Analysis of Reconfigurable Memories
John Maneatis	Precise Delay Generation Using Coupled Oscillators
Samuel Palermo	Design of High-Speed Optical Interconnect Transceivers
Arturo Salz	Incremental Tools for the Design and Verification of VLSI Circuits
Mark Santoro	Design and Clocking of VLSI Multipliers
Stefanos Sidiropoulos	High Performance Inter-Chip Signalling	Aeluros
Rich Simoni	Cache Coherence Directories for Scalable Multiprocessors
Mike Smith	Support for Speculative Execution in High-Performance Processors
Jeff Solomon	The ChipMap: Visualizing Large VLSI Physical Design Datasets (Images at 108 dpi for viewing, 2MB) (Images at full res dpi for printing, 32MB)
Don Stark	Analysis of Power Supply Networks in VLSI Circuits	Aeluros
Vladimir Stojanovic	Channel Limited High-Speed Links: Modeling, Analysis and Design
Jim Weaver	Measuring supply currents in printed boards
Gu-Yeon Wei	Energy-Efficient I/O Interface Design with Adaptive Power-Supply Regulation
Dan Weinlader	Precision CMOS Receivers for VLSI Testing Applications
Bennet Wilburn	High Performance Imaging Using Arrays of Inexpensive Cameras
Ted Williams	Self-Timed Rings and their Application to Division
Drew Wingard	High-Speed BiCMOS Memories
Vicky Wong	Characterizing the Parallel Performance and Soft Error Resilience of Probabilistic Inference Algorithms
Chih-Kong Ken Yang	Design of High-Speed Serial Links in CMOS
Evelina Yeung	High-performance & low-cost parallel links